The present invention relates to a semiconductor device and a method of manufacturing the same.
Recently, demands have arisen for higher integration degree of LSIs and higher operation speeds thereof. To achieve this purpose, the sizes of respective members constituting a transistor are proportionally reduced. However, a reduction in gate electrode width to about 0.1 μm poses the following problems.
FIG. 1 is a sectional view schematically showing an example of a conventional MOSFET. In FIG. 1, e.g., an SiO2 gate insulating film 2, and a gate electrode 3 prepared by heavily doping an n-type impurity such as phosphorus in polysilicon at 2×1020 cm−3 or more are sequentially stacked on one major surface of a p-type silicon substrate 1. An insulating gate sidewall 4 is formed on the side surface of the gate electrode 3 via a thermal oxidized film 10. An n-type impurity diffusion region 5 called an extension formed to be shallow below the gate sidewall 4, an n-type impurity diffusion region 6 formed to be deeper than the extension 5, and a device isolation region 7 made of, e.g., SiO2 are formed in the surface region of the substrate 1. And a metal silicide layer 8 is formed on the source/drain region by SALICIDE (Self Align Silicide) method to reduce the resistance value of the source/drain diffusion layers. In the MOSFET shown in FIG. 1, the extension 5 and the n-type impurity diffusion region 6 serve as source and drain diffusion layer. The metal silicide layer 8 is also formed on the gate electrode 3.
In the MOSFET shown in FIG. 1, the extension 5 must be controlled to have a high impurity concentration of about 1019 cm−3 and a small depth of 0.05 μm or less in order to suppress increases in short channel effect and electrical resistance value. To make the extension 5 shallow, the ion implantation acceleration voltage must be controlled to be as low as several keV. However, at a low acceleration voltage, the ion current decreases, so ion implantation cannot be complete within an actual processing time.
To prevent the leakage current from increasing by a reverse bias at a p-n junction, the distance must be typically set to 0.07 μm or more between the bottom surface of the metal silicide layer 8 formed in the surface region of the substrate 1, and the bottom surface of the n-type impurity diffusion region 6. The thickness of the metal silicide layer 8 is determined such that the parasitic resistance value of the source/drain diffusion layer becomes much smaller than the resistance value upon continuous application of a voltage to the gate electrode 3. For this reason, the metal silicide layer 8 must be formed to a predetermined thickness for obtaining lower resistance value, e.g., 0.05 μm or more. In other words, the n-type impurity diffusion region 6 is formed to position its bottom surface at a depth of 0.12 μm or more from the surface of the substrate 1. In this case, however, so-called punch-through may occur to flow a current even upon no application of any voltage to the gate electrode 3, i.e., in an OFF state.
As a structure for preventing the punch-through, an elevated source/drain structure shown in FIG. 2B is known.
FIGS. 2A and 2B are sectional views, respectively, schematically showing the steps in manufacturing a conventional MOSFET having an elevated source/drain structure. The same reference numerals as in the MOSFET shown in FIG. 1 denote the same parts in the MOSFET shown in FIGS. 2A and 2B, and a description thereof will be omitted.
In manufacturing a conventional MOSFET having an elevated source/drain structure, Si is selectively epitaxially grown on an n-type impurity diffusion region 5 to form an Si film 9, as shown in FIG. 2A. That is, a region serving as a source/drain diffusion layer is extended to above a substrate 1. The Si film 9 is also formed on a gate electrode 3. As shown in FIG. 2B, ions are implanted to form an n-type impurity diffusion region 6. Further, as described with reference to FIG. 1, a metal silicide layer (not shown) is formed to obtain a MOSFET. In FIGS. 2A and 2B, the gate electrode 3 is formed to be lower than a gate sidewall 4 in order to prevent electrical connection between the gate electrode 3 and the source/drain region due to the lateral growth of the Si film 9 formed on the gate electrode 3.
In the MOSFET formed in this manner, although the n-type impurity diffusion region 6 is formed to a satisfactory thickness, its effective depth, i.e., the depth from the surface of the substrate 1 is smaller than that in the MOSFET shown in FIG. 1. More specifically, according to the MOSFET shown in FIGS. 2A and 2B, a larger distance can be set between the bottom surface of the metal silicide layer (not shown) and the bottom surface of the n-type impurity diffusion region 6. By this method, however, Si grows not only on the n-type impurity diffusion region 5 shown in FIG. 2A but also in the lateral direction. As a result, the Si film 9 is also formed on a device isolation region 7, making it difficult to maintain an insulating state between adjacent transistors.
Although the nMOS has been exemplified, the pMOS also has the same structure as that of the nMOS except for an opposite semiconductor conductivity type. Therefore, the above-described problems also occur in the pMOS.